1. Field of the Invention
The present invention relates to nanowire-based devices, and more particularly, to nanowire-based static random access memory (SRAM) devices.
2. Description of the Related Art
In a static random access memory (SRAM) cell a combination of field-effect transistors (FETs) are used to store each bit. For example, in a six transistor (6T) SRAM design each cell contains six field-effect transistors (FETs). Other configurations vary the number of transistors, such as eight transistor (8T) and ten transistor (10T) SRAM.
In typical SRAM design layouts, there are many non-linear edges involved in the active area and gate definition masks. In conventional complementary metal-oxide semiconductor (CMOS)-based fabrication processes, the SRAM design layout is adjusted to obtain the smallest cell size possible so as to increase layout density, and hence great care is taken in the mask generation. However, since features involved in the active area definition and gate definition are not all the same size and/or orientation, these features are prone to lithography, etching and other process variations. Variations can adversely affect the performance of the completed device.
Therefore, SRAM cell designs that increase the layout density while effectively minimizing process variations would be desirable.